Non-volatile semiconductor memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile semiconductor memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM) devices. EEPROM devices differ from other non-volatile semiconductor memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value.
The threshold level of the enhancement transistor controls current flow through the transistor by application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state. This feature is identical to FET operation, except the floating gate in an EEPROM FET alters the threshold voltage dependent upon the presence of charge within the floating gate.
One type of EEPROM device utilizes a polycrystalline silicon or metal layer for the floating-gate electrode. Electrons are transferred to the floating-gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating-gate by an overlying control-gate electrode.
The EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating-gate electrode. The EEPROM device is erased by grounding the control-gate electrode and applying a high positive voltage through either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and transferred into either the source or drain regions in the semiconductor substrate.
Another type of EEPROM device utilizes an oxide-nitride-oxide (ONO) layer for the fabrication of the floating-gate electrode. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer.
Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous silicon nitride layer.
Non-volatile semiconductor memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within the ONO layer. This type of non-volatile semiconductor memory device is known as a two-bit EEPROM.
The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions. The structure and operation of this type of memory device is described in a PCT application having the International Publication Number of WO/07000 entitled xe2x80x9cTWO BIT NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPINGxe2x80x9d, the contents of which are fully incorporated herein by reference.
The fabrication of two-bit EEPROM devices utilizing an ONO gate structure presents numerous challenges. For example, it is difficult to fabricate an ONO layer without creating interface states that provide charge leakage paths within the ONO layer. Moreover, the ONO layer has the tendency to retain charge after each erase and program function, which may eventually lead to malfunction of the device. Accordingly, alternatives to ONO type two-bit EEPROM devices are desired to overcome these problems.
According to an aspect of the invention, a process is provided for making an array of two-bit floating gate transistors for a semiconductor memory device having a silicon wafer substrate with parallel rows of bit-line oxide and a tunnel layer on said silicon wafer substrate. The process comprises depositing a sacrificial layer on said tunnel layer, patterning the sacrificial layer to form isolation spacers between said parallel rows of bit-line oxide, depositing a floating gate polysilicon layer on said silicon wafer, and patterning said floating gate polysilicon layer to form isolation openings upon said rows of bit line oxide. According to a further aspect of the invention, the process further comprises removing said isolation spacers thereby forming isolation openings between said rows of bit-line oxide.
According to a further aspect of the invention, a process is provided for making an array of two-bit floating gate transistors for a semiconductor memory device is provided. The process includes providing a silicon wafer substrate having parallel rows of bit-line oxide, depositing a tunnel layer on the silicon wafer substrate, and depositing a sacrificial layer on the tunnel layer. The process further includes forming isolation spacers centered between the parallel rows of bit-line oxide by forming a first mask on the sacrificial layer, removing the first mask except leaving portions of the first mask over areas of the sacrificial layer where the isolation spacers are to be formed, removing the sacrificial layer from areas where the first mask is removed and leaving the sacrificial layer beneath the portions of the first mask that remain, and removing the portions of the first mask and leaving the isolation spacers on the silicon wafer substrate. A floating gate polysilicon layer is then deposited on the silicon wafer substrate to a thickness, and the isolation spacers are exposed by reducing the thickness. Adjacent isolated floating gates are then formed from the polysilicon floating gate layer by forming a second mask on the polysilicon floating gate layer, forming openings in the second mask layer centered upon the rows of bit-line oxide, and removing the polysilicon layer within the openings. Finally, the process includes removing the isolation spacers thereby forming isolation openings between the rows of bit-line oxide, removing the tunnel layer from within the isolation openings, and depositing a barrier layer on the substrate overlying the polysilicon floating gates.
According to a further aspect of the invention, the process includes exposing the isolation spacers is by reducing the thickness is chemical mechanical polishing and planarizing the polysilicon floating gate layer.
According to a further aspect of the invention, the process includes depositing the polysilicon floating gate layer to a thickness such that the polysilicon floating gate layer has a planar surface, and the exposing the isolation spacers by reducing the thickness is etching the polysilicon floating gate layer.